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Plasma surface processor atomic layer etching technology

Plasma surface processor atomic layer etching technology

With the decreasing of device size, semiconductor manufacturing industry has gradually entered the stage of atomic scale. Over the next 10 years, the acceptable range of characteristic size changes will be required to be within the order of three to four silicon atoms. The non-uniformity of device size will greatly affect the stability, leakage current and battery power loss of the whole device, resulting in device failure and yield reduction. In order to control the etching process accurately and improve the etching result, the atomic layer etching technique has been developed and studied. Although atomic-layer etching has been reported for more than 20 years, its rate of etching is relatively slow compared with traditional etching, and the low yield of etching process restricts its application in semiconductor manufacturing industry. However, with the development of three-dimensional structure fin-transistor technology, the homogeneity of atomic layer etching technology and the selection of ultra-high, plasma surface processor has been applied well in some key etching processes.   The atomic-layer etching technique of plasma surface processor (PSMP) is considered as a promising method to realize etching at atomic level, which is due to its self-limiting behavior. Self-limiting behavior means that the etching rate gradually slows to a stop with the increase of etching time or reactant input. An ideal atomic layer etching cycle can be divided into the following four stages: (1) inject reaction gas into the cavity, modify the surface of the material to form a single layer of self-limiting layer; (2) stop the reaction gas, and vacuum pump to remove the excess gas did not participate in the reaction; (3) High-energy particles are injected into the cavity to remove the single-layer self-limiting layer so as to realize self-limiting etching behavior; (4) Stop feeding high-energy particles, use the plasma surface treatment machine vacuum equipment pump to remove excess particles and etching by-products not involved in the etching.   For each cyclic reaction A and B in the actual atomic layer etching process, the ideal single-layer self-limiting etching process is difficult to be realized. Reaction A includes four different surface modification mechanisms, namely, chemisorption, deposition, conversion, and stripping. Reaction B mostly needs plasma assistance, and ions are used for anisotropic etching to obtain the etching structure with high aspect ratio. Plasma surface processors have been developed from atom etching to date and have been proven to be suitable for more than 20 different materials, including semiconductors, insulators and metals. It is believed that in the near future, it will be applied to more materials etching.  

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Neutral ion beam etching technique for plasma surface processor

Neutral ion beam etching technique for plasma surface processor

When the characteristic dimensions of LsI are reduced to less than 7nm, the inherent defects of plasma etching in conventional PLASMA surface processors will limit their further development and applications, such as charge accumulation and deep ultraviolet photon (VUV) radiation. The accumulation of charge caused by electron masking effect will lead to the accumulation of too much positive charge at the bottom of the etching pattern, resulting in charge-induced damage and the reduction of etching accuracy caused by the distortion surface of positive ion orbit. Deep ultraviolet photonic radiation not only intensifies the accumulation of positive charge, but also forms defects on the surface of etched substrate, thus affecting the etching reaction process of the surface. Therefore, it will increase the surface roughness of the substrate and the amount of etching on the side wall, and reduce the precision of etching. In addition, in order to accurately control the surface reaction in the etching process of plasma surface processor, the reaction particles involved in the etching need to have low energy, so as to improve the controllability and precision of the whole etching process.   In order to eliminate the above problems in the traditional plasma etching and plasma etching process provides low energy particle surface processor, neutral particle beam etching technique has been developed and obtained a certain development, with the traditional pulse plasma etching and plasma etching and atomic layer etching system, plasma surface treatment machine neutral particle beam etching technology development suited to its own system. So far, the neutral particle beam etching system is mainly divided into three types: electron cyclotron resonance plasma, DC plasma and inductively coupled plasma plus parallel carbon plate. For the electron cyclotron resonance plasmas and dc plasmas, the neutral particle beam is formed by the charge transfer of positive ions, with low neutralization efficiency (about 60%), while the particle beam has high energy (>100eV). This low neutralization flux and high-energy particles, leading to the low, etching etching rate and selectivity, so it is not suitable for etching process is different from the former two ways, the plasma surface treatment machine parallel carbon plates with inductive coupling plasma way, neutral particle beam is formed by anion separation electronics.   In the power shutdown stage of plasma pulse technology, a large number of negative ions are generated and pass through parallel carbon plates to form neutral particle beams by separating electrons. Compared with the positive ions, when by parallel plate carbon anion is more likely to be neutral, mainly because of negative ion separation electron energy is much less than positive ion charge transfer, so the neutralization efficiency is much better than the cation, anion chlorine anion neutralization efficiency can be close to one hundred percent, for example, while the neutralization efficiency of chloride ions is only about 60%. In addition, for the inductively coupled plasmas with parallel carbon plates, the bias is applied to the bottom parallel carbon plates, so the negative ion beam energy can be accurately controlled to produce the neutral particle beam with low energy and high flux. Compared with the former two methods, the neutral particle beam etching technique of plasmas coupled by induction and parallel carbon plate has a better application prospect.   As the chip feature size is gradually reduced, the requirement of etching process will be higher and higher. When the feature size is reduced to less than 7nm, the need for accurately controlled anisotropic etching process becomes increasingly urgent. The neutral particle beam etching plasma surface treatment machine basic won't produce charge accumulation and ultraviolet photons (vacuum) radiation, and the resulting particle reaction energy is very low, so it is possible that plasma surface treatment machine will be very suitable for 7 nm below fins fet etching of silicon substrate, and under 5 nm carbon nanotubes or graphene devices accurate noninvasive etching.

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Plasma surface processor gas cluster ion beam etching technique

Plasma surface processor gas cluster ion beam etching technique

Plasma surface processor gas cluster ion beam etching has a series of characteristics that traditional plasma etching does not have. In conventional plasmas, electrons and ions have a wide energy distribution, and a few high-energy particles can penetrate several layers of atoms to damage the substrate during etching on the target material. Therefore, how to optimize the energy distribution of plasma ions in plasma surface treatment is always a development direction of plasma etching technology.   The gas cluster ion beam has an outstanding advantage in this respect. A gas cluster is a relatively stable aggregate composed of several to tens of thousands of atoms or molecules under the action of physics or chemistry. Gas clusters can be ionized under electron bombardment, and ionized gas clusters can obtain great kinetic energy under the action of electric field, and can also be filtered under the action of magnetic field, so as to obtain gas cluster ion beam with more concentrated energy distribution. Plasma surface processor gas cluster ion beam can obtain high energy under the action of accelerating electrode, form high energy density in a local area, and excite many kinds of physical and chemical reactions near the target material surface. But the velocity of each particle in the cluster is interphase, and the average energy of each particle is low. Therefore, at the same average energy as the traditional plasma, the energy of the particles is much better than the plasma, and will not cause damage to the deep atoms of the target material during the process of reacting with the target material.   This advantage makes gas cluster ion beam can be used well in many aspects. Examples include surface smoothing, surface analysis, shallow injection, film deposition, particle removal, etching, etc. With the increase of energy, different reactions such as gas cluster deposition, gas cluster etching and gas cluster shallow injection are introduced. The specific methods of producing clusters by PLASMA surface processors include gas accumulation, ultrasonic expansion, laser evaporation, magnetron sputtering, ion sputtering, arc discharge, electroinjection liquid metal method and helium droplet extraction method.

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Plasma surface processor Polysilicon gate etching

Plasma surface processor Polysilicon gate etching

When the CMOS process extends to 65nm or below, the etching manufacturing of plasma surface processor gate faces many challenges. As a key technology to control channel length, the pattern of polysilicon gate is closely related to the performance of the device, which affects the whole body. Moore's law promotes yellow light graphics technology from 248nm wavelength light source technology to 193nm wavelength light source technology. This transition was achieved in 2012 with a graphics resolution of 30nm. However, the chemical composition of 193nm photoresist is very different from that of 248nm photoresist, and its anti-etching ability is poor under harsh plasma environment. In order to ensure the exposure process window, the 193nm photoresist is needed to be thinner. In this case, grid graphic dimension control, such as feature size, line width uniformity, wall Angle, side wall shape (concave, protruding) and line width roughness, etc. are all process parameters requiring strict control.   The problem of grid wall roughness can be easily caused by the inorganic hard mask (generally silicon nitride) etching method used by traditional polysilicon gate plasma surface processor. On the other hand, in order to solve the depletion layer problem of polysilicon gate, the polysilicon film layer needs to be doped in advance, which is generally phosphorus doping. Due to the concentration of the doping on the upper part of the polysilicon by ion implantation through the plasma surface processor, severe necking phenomenon occurs when the polysilicon gate is used to remove the hard mask with hot phosphoric acid. Because of the above problems, polysilicon gate etching turned to soft mask etching after 65nm. The etching of traditional polysilicon gate is dominated by halogen gas elements, such as Cl2 and HBr. Predoped polysilicon also has shrinkage phenomenon in halogen gas etching. Han Guo-Lee et al. explained this phenomenon in literature by doping and the coulomb forces of atoms or molecules of halogen gases. The coulomb force of mutual attraction between N-type doped phosphorus or arsenic and chemisorbed halogen gas will increase the etching rate of polysilicon doped plasma surface processor, thus causing shrinkage phenomenon. Zhang et al. studied the effect of HBr/Cl2, HBr/O2 and CF4 on the etching rate of N-type doped polysilicon. The difference of etching rate of CF4 gas in N-doped polysilicon and undoped polysilicon is small, within 5%. The etching rate difference of HBr/O2 is more than 20%, while the etching rate difference of HBr/Cl2 is between the two, about 13%. Therefore, it is a better choice to use CF4 when etching n-type doped polysilicon located in the upper half of polysilicon gate. Because poly gate lithography to stop on the gate oxide silicon, so when using the CF4, gas was fed main etching step after etching the upper half of doped polysilicon, etching the remaining 20% of the lower part of the polysilicon gate etching steps we need to adopt gets/O2 gas etching, in order to realize the plasma surface treatment machine polycrystalline silicon etching high selectivity of gate oxide silicon. As mentioned above, the etching rate of HBr/O2 on N-type doped polysilicon is 20% higher than that of non-hetero polysilicon, which is prone to generate neck shrinking effect. Therefore, the over-etching amount of HBr/O2 should be strictly controlled, generally 30% is better. Too little over-etching amount will lead to long feet on the side wall bottom of the polysilicon gate, and too much over-etching amount will lead to the enhancement of upper neck shrinking effect.   Although HBr/O2 etching process with a higher etching selection ratio for gate silicon oxide is used in plasma surface treatment, it is still easy to cause silicon perforation and silicon damage. The occurrence of silicon perforations is generally due to excessive etching in the main etching step, the touch of gate silicon oxide, or the decrease of etching selection ratio due to the insufficient optimization of HBr/O2 process. However, the Silicon damage caused by polysilicon grid etching is usually detected by transmission electron microscope without corrosion Recess. The cause is not directly related to the etch selection ratio. Due to the decrease of saturation current caused by silicon damage, it is necessary to strictly control the bulk silicon damage during any polysilicon gate etching. Principle of bulk silicon damage caused by polysilicon gate etching in plasma surface treatment Due to the consideration of equivalent silicon oxide thickness, the gate oxide layer is as thin as 1~2 nanometers in the process below 65nm. In HBr/O2 plasma, HBr decomposes hydrogen ions, because the mass of hydrogen ions is very small, under the acceleration of the electric field, high-energy hydrogen ions can pass through gate silicon oxide and inject into the bulk silicon up to 10nm deep, causing dislocat

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Influence of step height of plasma surface processor on polysilicon gate etching

Influence of step height of plasma surface processor on polysilicon gate etching

In addition to the effect of the surface etching of plasma surface processor on the size of polysilicon gate, the surface topography fluctuation caused by shallow groove isolation also has a significant effect on the size of polysilicon gate. The height of shallow grooved isolated steps characterizes the surface morphology of the wafer before polysilicon growth. Due to the flat growth of the furnace tube polysilicon, the positive step height (the upper surface of the shallow trench isolation silicon is higher than the bulk silicon active region) will lead to the thickening of the polysilicon near the shallow trench isolation region, thus affecting the side wall Angle of the polysilicon gate. At the positive step height, after the main etching step of the plasma surface processor polysilicon gate etching, the side wall of the polysilicon gate located in the isolation zone of the shallow groove is obviously more inclined than the active zone, and the characteristic size is also obviously larger than the active zone.   Even if the plasma surface treatment machine's main etching step USES gases that produce less polymerization byproducts, vertical gate wall cannot be formed in the shallow trench isolation zone, and this difference in side wall will remain until the etching is complete. The side wall Angle of the polysilicon gate near the shallow groove isolation is only 86°, while the side wall Angle of the polysilicon gate located in the center of the active region reaches 89°. Therefore, the difference of polysilicon film thickness leads to the difference of gate side wall Angle, while the difference of gate side wall Angle leads to the difference of feature size.   Under different characteristic sizes of active zones, the isolated step height of shallow trench will be different. The load caused by the difference of density in the source area during the chemical mechanical grinding after the shallow groove isolation will lead to the difference of step height, which will affect the difference of characteristic size and Angle of polycrystalline silicon etching. The relationship between the polysilicon height and the step height under different width of the fed region shows that the size of the fed region is closely related to the step height during gate etching. With different width of the source region, the characteristic dimensions of the optical polysilicon and the polysilicon with surface morphology before and after exposure and etching show that the width of the source region is different, and the etching deviation of the plasma surface processor will also be different.

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Double graphic etching of polysilicon gate for plasma surface treatment machine

Double graphic etching of polysilicon gate for plasma surface treatment machine

In polysilicon graphic definition, in addition to the characteristic size of the line itself, the graph at the end of the line also needs to be strictly controlled. Different from the center of the line, due to the limitation of yellow light process, the side wall of photoresist at the end of the line is tilted out, and it is etched from three directions when the plasma surface treatment machine etches, so the photoresist recedes rapidly. In this industry, the precision of etching process to the line end graphics is evaluated by the ratio of the characteristic size difference before and after etching and the characteristic size difference before and after etching with the plasma surface processor in the center of the line, which is called line end retraction.   In general, the smaller the retraction at the end of the line, the better, indicating that the distortion at the end of the line is controlled within a small range. It is well known that polysilicon gate lines cross the active region to form devices. If the end of the polysilicon gate line falls back too much during the etching process of the plasma surface treatment machine, the gate length will not be enough to cross the active region, and the silicon oxide in the shallow groove isolation area will be damaged in the subsequent process, which will cause the exposed active region as the channel to form damage and cause device failure.   It is found that the retraction of the end of the line is closely related to the initial etching process defined by graphic etching, and the retraction performance of the end of the line is very different when the gas is etched with different anti-reflection layers at the bottom. At present, there are mainly HBr/Cl2 and fluorine base gas etched by plasma surface treatment machine. Using the bottom anti-reflection layer etching process of fluorine-based gas, the regression degree of the line end is far less than that of HBr/Cl2 etching process. This is because in the HBr/Cl2 etching process, the VUV will change the surface properties of the photoresist, and the fracture of the photoresist polymer molecules will make the photoresist remelt and shrink, making the regression of the end of the line more violent. Therefore, in the initial etching step of the graphic definition, the use of fluorine-based gas can accurately control the transfer of the graphic. But with miniature device, demand of polysilicon gate 'distance is smaller and smaller, at this moment just by LES has been unable to meet the requirements of process control, the introduction of dual graphics cutting technology is a good way to solve this problem, the double graphics process as early as 2010 years ago have been put forward, samsung technology was at the university of new Mexico lawsuit, since then, double graphics technology invention got rapid development, also in the field of domestic made a lot of layout on the intellectual property rights.   The industry has introduced a dual graphics process in the 28nm process to avoid excessive shrinkage of polysilicon line ends. Long line shapes are first formed through the first exposure and etching, often referred to as P1. Then, the second exposure process is made. Sandwich structure process with anti-reflection layer at the bottom containing silicon is generally adopted. In other words, the lower layer is deposited by rotary coating process to achieve the purpose of flattening. Then spin coating intermediate layer containing silicon bottom anti-reflection layer; The exposure process of rotating photoresist and cutting hole. Cutting polysilicon grids by an etching process is often referred to as P2. This dual graphic technique effectively avoids the microform limitation of yellow light exposure in both the length and width of the gate in the first graphic technique. At the same time, through the optimization of etching cutting process, that is, adding gas that can produce heavy polymer into the etching gas of plasma surface treatment machine, the head-to-head distance of polysilicon gate can be reduced to less than 20nm, which meets the need of continuous microminification in the active region.   Adopts double graphics etching process, the cutting process of process window is to be considered, usually all graphics cutting process by using the design rules make all fall on the silicon oxide, which in the hard mask cutting hard enough in the steps of etching, in order to achieve the purpose of cutting completely, increase craft work window. However, if there is no design rule to avoid it, that is, if there is an area where both graphics are exposed and the substrate below the polysilicon is designed in an active region, then the over-etching amount should be controlled in the cutting process to avoid the damage of the underlying silicon substrate. When the size is further miniaturized, the depth-width ratio of the cutt

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