图片名称

NEWS

Popular Articles

Contact Us

图片名称
图片名称

Service Hotline

13632675935

CRF

TEL：13632675935

E-mail：shaobo@sfi-crf.com

Address: 1303, Building 3, Manjinghua Science and Innovation Workshop, No.6 Songjiang Road, Songgang Street, Bao'an District, Shenzhen, China.

Contact hole etching process for the lower electrode of phase change memory for plasma Surface processor

Contact hole etching process for the lower electrode of phase change memory for plasma Surface processor

The size of the "heater" in the storage unit of the PHASE-change memory is critical to the performance of the device, and the smaller size means that the lower electrode contact has a higher current density, higher heating efficiency, and a smaller area of the phase-change material. The structure and process flow of the knife-edge silicon nitride electrode contact with GST as phase change material, which can form the lower electrode contact with the size of less than 20nm along the direction of the position line. According to the cutting sequence of Titanium nitide in U-shaped groove, lithographic segmentation and plasma surface processor etched after etching in the contact hole of the lower electrode are two technological processes. The lithography segmentation process uses the distance between the two ends of the photoresist to define the segmentation zone. Then, the lower layer of the film is removed successively. The upper surface and side wall of the U-shaped groove are removed, and the bottom layer is also cut accordingly. The process is simple and the cost of the hood is low, but the limitations of lithography may lead to the Shortening of the Line End (LES), which can lead to lateral parietal titanium loss. When the graph is further miniaturized, the effect becomes more significant and even causes the graph to fail. The lithographic pattern of etching and cutting process is a complete straight line, and the bottom nitriding will not be cut, so it is necessary to add additional silicon nitride cutting process after etching by plasma surface processor of plasma cleaning machine with contact hole of the lower electrode. This method requires at least two masks, which is of high cost. The advantage is that the lithography process window is large, and the control ability of the size of the lower electrode contact along the direction of the word line is strong, which facilitates the further reduction of the size of the lower electrode contact. The requirements of the two processes for the etching of plasma surface processor in the plasma cleaning machine with lower electrode contact holes are appropriate contact size, vertical TI nitriding profile shape and no TI nitriding residue at the bottom of u-shaped groove. After the organic substrate in the trench is removed by the plasma surface treatment with the plasma cleaning machine, there are two schemes of isotropic and anisotropic plasma etching for the titanium nitride silicon oxide in the lower layer. If isotropic etching is adopted (such as high pressure strength, low rf power combined with high ratio CF4 for silicon oxide etching or high ratio Cl2 for titanium nitridation etching), the lithographic segmentation process can effectively ensure that there is no titanium nitridation residue at the side wall and bottom of the groove, but it also brings side effects such as oblique profile shape and serious CD loss. In addition to the above problems, there are titanium nitride and even silicon oxide residues on the side wall in the cutting method after the plasma surface processor etching in the plasma cleaning machine. After the etching time is prolonged, the residue is removed but the top of the titanium nitride is seriously damaged. If anisotropic etching is used (e.g., low pressure strength, high bias power combined with C4F8/Ar for silicon oxide etching or Cl2/N2 for titanium nitide etching), both processes have better CD loss and profile shape, with serious substrate material loss as a side effect. Organic substrate material are removed, the oxidation of anisotropic silicon etching will remove groove at the top, but at the bottom of the film in the lateral wall with residual, especially the corner if the silica/titanium nitride choice than below 15:1, the plasma cleaning machine plasma surface treatment machine increase etching time will open at the bottom of the titanium nitride cause severe loss of substrate materials. However, the plasma etching process of plasma surface processing machine with too high selection ratio will cause more inclined slope shape and the uniformity is more difficult to control. The two etching schemes have their own advantages and disadvantages. Because CD control is important for the further miniaturization of graphics and mass production, the industry tends to adopt the anisotropic etching scheme of plasma surface processor in plasma cleaning machine. Therefore, in order to resolve the conflict between titanium nitrite residue and selection ratio, a partial removal scheme of organic substrate was proposed. In this scheme, by controlling the opening time of organic substrate, enough organic matter is left in the trench to protect the titanium nitrite at the bottom, so as to avoid the conflict between the two demands of etching directivity and selection ratio. Therefore, CF4/CHF3, an etching formula with a low selec

MORE +
GST etching process of phase change memory of plasma Cleaning Machine

GST etching process of phase change memory of plasma Cleaning Machine

GST is a widely used phase change material, and its plasma cleaning machine etching process is unique to phase change memory. 1. Plasma cleaning machine GST etching gas screening As the core material of PHASE-change memory, THE volume of GST directly affects the electrical performance of the device, so the integrity of GST films is very important. The influence of Cl, F and Br3 different halogen gases on GST etching profile of plasma cleaning machine was studied. The main etching agent containing bromine gas showed less damage to GST morphology than oxygen gas or fluorine gas. The Ar and He as dilution gas had less influence on the GST diagrammatic form, but in the graph with 4 wires as a set, the load of the edge and center graph was smaller when using He. When Ar is used, the load is relatively significant, and this difference may originate from the significant quality difference between Ar and He. 2. Hard mask (Titanium nitride) profile shape control Titanium nitride is generally used as a hard mask for GST etching, and its profile shape directly affects the contour of the underlying GST. Chlorine gas (Cl) in the plasma cleaning machine is mostly used for titanium nitride etching. In the influence of adding BCl3 and He to chlorine gas on the profile shape of titanium nitride, it can be seen that although adding He can bring a higher optoresistance selection ratio, the etching surface of its titanium nitride is obviously more tilted than adding BCl3. 3. Post-etching treatment In general, after dry etching such as plasma cleaning machine is completed, a step of acid or alkaline wet cleaning is introduced to completely remove the by-products formed by plasma etching on the wafer to avoid secondary reactions. GST is a kind of metal alloy, any acid or alkali will cause serious corrosion, so GST plasma etching can only use low concentration of acid (or alkali) wet cleaning agent, GST etching produced by the metal elements of the by-products cleaning effect is poor. As a result, a plasma cleaning machine after etching processing (Post Etch Treatment) technology was introduced, after complete the GST and remove photoresist etching, join step shorter for fluoride gas etching agent (CF4, SF6 and NF3) etching formula, using fluoride gas can activate the GST etching by-products characteristics, can obviously improve the effect of the wet cleaning.

MORE +
Mold plasma cleaning machine

Mold plasma cleaning machine

Plasma cleaning machine is a new type of cleaning machine, it can use plasma arc to clean mold surface dirt, to achieve the purpose of cleaning mold. In the process of use, the mould is polluted due to the comprehensive action of rubber, coordination agent and vulcanization release agent, so the scale forming mould needs to be cleaned regularly. Chemical cleaning method is easy to corrode mold surface and cause environmental pollution, mechanical cleaning method is contact cleaning, easy to damage the mold surface and generate residual stress. Although the new cleaning technologies, dry ice cleaning and laser cleaning, overcome the shortcomings of traditional cleaning methods, they also have their own defects. The disadvantages of traditional cleaning methods compared with other cleaning methods are overcome by plasma cleaning machine. With the increase of plasma output power, the surface temperature of the mold sample increases, decreases with the acceleration of plasma motion speed, and decreases slightly with the increase of matrix thickness. When cleaning strength is greater than the bond or cleaning force per unit area is larger than the stick relay on the per unit area, the adsorption on the surface of the substrate, contaminant particles can overcome the constraints of cohesive force and loss, in order to prevent the substrate surface, the plasma arc burns in cleaning ability than pollutants and the cohesive force between the substrate surface, interface temperature should be below the liquidus temperature of substrate. At present, due to the appearance of plasma cleaning machine technology, it has been widely used in many fields such as optics, electronics, materials, life science, polymer science, biomedicine and so on.

MORE +
Semiconductor principle of vacuum plasma cleaning machine

Semiconductor principle of vacuum plasma cleaning machine

With the development of modern electronics technology, Flip - ChipBond semiconductor packaging technology has been widely applied, but as a result of the front-end technology requirements, the machining process will inevitably some residual organic matter or other contaminants on the base material, in the baking process, originally under the pad of gold plating Ni element will be moved to the surface layer, without removal of pollutants, leads to bump on the semiconductor chip in Flip - ChipBond technology with the whole process of pad bonding effect is poor, adverse consequences. Traditional cleaning processing technology such as CFC cleaning, ODS cleaning, due to environmental pollution, high cost, limited the further development of modern electronic equipment technology, especially precision mechanical equipment manufacturing semiconductor chips, so the plasma cleaning machine dry cleaning, especially plasma cleaning technology is the current development trend. There are two cleaning methods of vacuum plasma cleaning machine. One is the reaction of plasma on the material surface, common gases, such as argon (AR), nitrogen (N2), etc. The other is that the oxygen radical has undergone chemical changes. The common gases are hydrogen, oxygen, and so on. Vacuum plasma cleaning machine plasma through impact to destroy the ionic bond of organic matter, so as to remove surface pollutants. When the working pressure is low, the higher the ion energy, the greater the kinetic energy and the greater the impact force. If the physical reaction is used for cleaning, it reflects the lower working pressure and the stronger the actual cleaning effect. Selecting argon gas as the advantages of vacuum plasma gas cleaning, cleaning principle of argon plasma technique is to use particle mechanical cleaning, argon gas is inert gas, in the process of cleaning will not cause chemical reaction products and gas, avoid secondary pollution, as the front-end processing residual residue can be reasonably clear, in the process of making a semiconductor can be fused in the bonding process. Compared with the traditional wet cleaning process, the plasma technology of vacuum plasma cleaning machine is environmentally friendly and cheap.

MORE +
Application of etching in plasma cleaning machine and introduction of new magnetic memory

Application of etching in plasma cleaning machine and introduction of new magnetic memory

Magnetic Random Access Memory (MRAM) is a type of Memory with Magnetic Tunnel Junction (MTJ) as its core component. The magnetic tunnel junction is a sandwich structure of ferromagnetic Layer/tunnel barrier Layer (metal oxide, such as MgO)/ ferromagnetic Layer. One Layer of ferromagnetic material is called the Reference Layer, whose magnetization direction is fixed, while the other Layer is called Free Layer, whose magnetization direction can be changed by the external magnetic field or Polarized Current. When the magnetization directions in the fixed layer and the free layer are the same, the MRT junction presents low electrical positive. When the magnetization directions are different, the MRT junction presents high electrical resistance. This phenomenon is called the tunneling magnetoresistance effect.   Conventional magnetic memory, which uses an external current to generate a circular magnetic field to change the direction of free-layer magnetization, has been replaced by Spin Transfer Torque (STT) magnetic memory, which has large storage units and no read-write speed advantages over other memory. The so-called spin transfer moment refers to the change in the magnetic moment of atoms in the ferromagnetic layer when the spin polarization current passes through the nano-sized ferromagnetic layer. This means that the magnetic tunnel junction can be driven directly by the current. After the electron spin polarization, a torque is generated on the ferromagnetic atom to change the magnetization direction in the ferromagnetic layer to realize the change of resistance. Therefore, the area and performance of the memory can be improved. The 1T1M (One One MTJ) magnetic memory consists of a magnetic memory in which a magnetic tunnel junction is visualized using a few bytes or bytes in the middle of the Transistor.   Spin transfer torque of magnetic memory are made in standard CMOS logic circuit after a period of metal connection layer embedded storage unit (magnetic tunnel junction), integrated with the spin transfer torque of the magnetic tunnel junction logic after a period of electric and magnetic tunnel junction of general process, obviously, the magnetic tunnel junction etching on device performance is very important. Ion Beam Etching (IBE), inductively coupled plasma Etching (ICP), REACTIVE Ion Etching (RIE) and other systems are the main Etching technologies used at present. It is worth noting that the shape of magnetic tunnel junction not only affects device performance, but also significantly affects the etching process of plasma cleaning machine. For example, the etching of cylinder or ring pattern is relatively simple.   At present, it has been reported that the materials used in magnetic tunneling junction contain Fe, Co, Ni, Pt, Ir, Mn, Mg and other metal elements and are generally made of 5-10 layers of single-layer materials (alloy or metal oxide) at the order of 1nm. Therefore, the challenges of plasma etching in the plasma cleaning machine of magnetic memory include: 1. Traditional reactive plasma (RIE) is confronted with the non-volatile problem of metal etching by-products; 2. The super-thin stacked structure of single layer materials has a high requirement for etching selection ratio and directivity; 3. The halogen gas commonly used in metal etching can corrode ultra-thin metal material layers easily. In particular, the barrier is mainly metal oxide and its thickness in the vertical magnetic tunnel junction is less than 3nm, which is prone to corrosion and therefore affects the electrical isolation of the fixed layer and the free layer (Electrically Isolated). 4. Process temperature limit, for example, the magnetism of most metal materials will decrease after exceeding 200°C. This temperature limitation is not only manifested in the shrinkage of the temperature window of the corresponding material etching formula, but also in the low temperature forming of the hard mask material etching resistance is generally lower.   Therefore, IBE as the representative of ion milling technology without corrosive side effect always occupies a place in the etching of magnetic tunnel junction plasma cleaning machine. The problem it faces is that the metal material stripped in the etching process may be redeposited in the side wall, and the subsequent cleaning process is difficult to remove, which will greatly affect the performance of the device. If it is deposited on the side wall of the barrier layer, it will directly cause short circuit. In addition, the shadow effect of secondary sediments will cause the etching shape to become more and more oblique with time. The overall tilt and rotation of the wafer can ameliorate this problem, but it also severely restricts its productivity. The uniformity and orientation of the ion beam at the 300mm wafer level also remain to be resolved. Compared with the plasma

MORE +
Plasma cleaner manufacturers to share the development of integrated circuits

Plasma cleaner manufacturers to share the development of integrated circuits

In 1958, the United States, Texas instruments, shows the start of the world's a piece of integrated circuit, wire connect five electronic components in, it marks the world into the era of integrated circuits, from now on, in 1959, Martin @ pull bell LABS (Martin Atalla) and the prosperous khan (Dawon Kahng) developed the first insulated gate field effect transistor (FET) their success factors is by controlling the surface state makes the influence of electric field can penetrate into the semiconductor materials. In studying thermally growing silica, they found that in the structure of the metal layer (M), oxide layer (O insulation), and silicon layer (S semiconductor), these "surface states" are greatly reduced at the junction between silicon and its oxide. In this way, the applied electric field can affect the silicon layer through the oxide layer, hence the name MOS. The research was halted because the original MOS devices were slow and failed to solve the problems faced by telephone devices. But researchers at Fairchild semiconductor and RCA recognize the advantages of MOS devices. In the 1960s, Karl Nininger and Charles Meuller built MOS transistors at Radio Corporation of America. Fairchild semiconductor's C.T.Ah built a MOS tetrode with a control electrode, and MOS transistors began to be used in the development of integrated circuit devices. 1962, Fred heyman (Fred Heiman) and Steven Stan (Steven Hofstein) in the radio corporation of America has made an experimental single chip integrated circuit composed of 16 transistor devices, in 1963, an article written by fairchild with research and development laboratory, along with Frank than lars (Frank Wanlass) in the paper show that, when in connection with complementary symmetry circuit configuration and n - p - channel is the channel of MOS transistor to form the logic circuit (today called CMOS, complementary field effect tube), The power consumption of this circuit is close to zero. This invention was patented by Frank Van Las. CMOS technology laid the foundation for low-power integrated circuits and became the mainstream production technology of digital integrated circuits today. In 1963, in defining and developing standard logic circuits, the transistor-transistor logic (TTL) integrated circuit was established as the standard logic module popular in the 1960s and 1970s due to its advantages in speed, cost and intensity. In 1964, hybrid microcircuits reached their peak production, and the multi-chip SLT packaging technology developed for the IBM Systems /360 computer series entered mass production. In the same year, commercial MOS integrated circuits were introduced, and General Microelectronics used the MOS process to achieve a higher level of integration than bipolar integrated circuits, and used the technology to create an original calculator chipset. In 1968, Federico Faggin and Tom Klein improved the reliability, speed, and package integration of MOS integrated circuits using a silicon gate structure instead of a metal gate. Fagg designed an original commercial silicon gate integrated circuit (Fairchild 3708). In 1971, Intel engineers created the first single-chip microprocessor (CPU), the I4004, to reduce the number of chips needed to design an arithmetic unit. In 1974, the integrated circuit used for LCD digital watches was the original product (SoC) that integrated the entire electronic system onto a single silicon wafer. In 1978, user programmable logic devices (programmable row logic) were born. In order to allow customers to quickly define logic functions, John Birkner and H.T.Cooer of Monocle developed easy-to-use programmable row logic (PAL) devices and software tools. In 1979, the monocle digital signal processor was born. Bell LABS single-chip digital signal processor DSP - 1 device structure makes the electronic switch system more perfect, in the same period, Texas instruments developed in programmable DSP1965 fairchild semiconductor r&d director Gordon Moore (Gordon Moore) had written an internal document, he compiled 5 groups of product development from 1959 to 1964 and with low cost of chip integration and a single device in graphs, then draw a line through these points. From this graph, Gordon Moore found that each new chip contained roughly twice the capacity of its predecessor, and that each new chip was produced within 18-24 months of the previous one. If this trend continues, computing power will rise exponentially relative to the time period. Moore's observation is now known as Moore's law. Over the next decade, he predicted, the number of devices on chips would double every year, reaching 6,500 by 1975. "For integrated circuits, cost-cutting is very attractive," he said. The cost advantage will continue to grow as technology advances to enable the integration of more and more circuit functions on a single chip. In 1975, has joined Intel Gordon M

MORE +
< 1...404142...132 > proceed page
图片名称

CRF

National Service Hotline

136 3267 5935

Contact Email

shaobo@sfi-crf.com

Address:1303, Building 3, Manjinghua Science and Innovation Workshop, No.6 Songjiang Road, Songgang Street, Bao'an District, Shenzhen, China.

图片名称

Add WeChat
Get related information

Links

Apply to exchange friend links

Copyright © Shenzhen Chengfeng Smart Co.

京ICP备10002622号-38

粤公网安备 44030602005200号

图片名称

Cheng Feng Zhi Zuang a focus on plasma research and development for 20 years

We

The services of

Inquire for free sample testing

1-to-1 program customization

24-hour online after-sales service

Source manufacturer

Get the program
%{tishi_zhanwei}%
图片名称

Scan the code for information

诚峰智造